1. FIELD OF INVENTION
This invention pertains to improving performance of compound semiconductor devices, generally, and more particularly to enhancing both DC and AC performance of field-effect transistor devices. Also provided is a method for efficiently producing these enhanced performance devices at lower cost than existing methods. In the preferred embodiment, carbon (C-ion) implants in gallium arsenide (GaAs) -based transistors are utilized both to sharpen the profile of a silicon (Si-ion) n-type channel and to minimize parasitic capacitances associated with buried p-regions. Use of the invention allows for improved DC and AC (high frequency) functioning of metal semiconductor field effect transistors (MESFETs), junction field effect transistors (JFETs) and other similar devices. Further, use of the methods described in fabricating the preferred embodiments will permit more efficient and less costly fabrication than currently used in competing methods while using the same manufacturing technologies currently available and in use.
2. Description of the Related Art
From Ion Implantation in Gallium Arsenide MESFET Technology, Joel P. de Souza and Devendra K. Sadana, IEEE Transactions on Electron Devices, Vol. 39, No. 1, Jan. 1992: "The channel length is one of the most important parameters that determines the switching frequency of a MESFET. However, when the channel length becomes shorter than 1 .mu.m the subthreshold conduction begins to increase and a drop in threshold voltage to negative values occurs. These effects are called short-channel effects. These effects, in principle, can be alleviated by forming a buried p layer underneath the channel of a MESFET. The p layer compensates the extended carrier tail present in the dopant profile in the channel and enhances the device transconductance. In addition, the threshold voltage uniformity across the wafer is improved . . . . To create a buried p layer, Be.sup.+ or Mg.sup.+ are typically implanted to doses of 5.times.10.sup.11 to 2.times.10.sup.12 cm.sup.-2 at energies sufficient to place the projected range of the p species at depths &gt;2-3 times that of the n implant . . . Ideally, the maximum p dose should correspond to a value which creates a fully depleted p-implanted region. Low p doses are typically 100% active after a &gt;760-800.degree. C. RTA (Rapid Thermal Anneal) or furnace anneal. . . . The precise mechanism by which the tail compensation of n dopants occurs in the presence of a p-type dopant is more complicated than what appears at a first glance. The compensation behavior is different depending on whether the p implantation is annealed before or after the n implantation and whether or not a Si.sub.3 N.sub.4 cap is used during subsequent annealing." From the Conclusions, Id,: ". . . Obviously, optimization of RTA processing for GaAs IC's (integrated circuits) would require better understanding of materials-related phenomena in GaAs." (emphasis added)
There has been an inherent trade-off between optimizing the DC and AC (high-frequency) performance of GaAs MESFETs or JFETs that incorporate a p-type implant below the n-type channel region. This trade-off relates to the need for a high implant dose to realize good carrier confinement, and thus good DC performance (by minimizing short channel effects), and a low dose implant to minimize the gate-to-source capacitance (C.sub.gs) from the resulting pin junction at the bottom of the channel. Looking to the equations which describe the basic physics of Applicants' device:
g.sub.m =K (V.sub.g -V.sub.t) PA1 f.sub.t =g.sub.m /(2.pi.X.sub..gamma..SIGMA.) PA1 K=(Z.epsilon.m)/(2aL.sub.g)
where
and
______________________________________ V.sub.g is the gate voltage V.sub.t is the threshold voltage of the MESFET C.sub.gs is the capacitance between the gate electrode and the source electrode .epsilon. is the dielectric constant of the semiconductor substrate m is the mobility of the carrier a is the thickness of the active layer L.sub.g is the gate length Z is the gate width g.sub.m is the transconductance f.sub.t is the cut-off frequency ______________________________________
With greater conductance, g.sub.m, the MESFET has higher current amplification and can drive a greater capacitive load at a high speed. Moreover, with a higher cut-off frequency, f.sub.t, the MESFET can switch at a higher speed. U.S. Pat. No. 4,717,685, Method for Producing a Metal Semiconductor Field Effect Transistor, Shigeru Nakajima, issued January 5, 1988, column 1, line 54-column 2, line 30.
Any increase in C.sub.gs will degrade the high-frequency performance by reducing both the unity gain cutoff frequency (f.sub.t) and the maximum oscillation frequency (f.sub.max). Unity current gain cutoff frequency, f.sub.t, and maximum oscillation frequency, f.sub.max, are related to each other and the MESFET parasitics as follows: EQU f.sub.t =g.sub.mi /2.pi.(C.sub.gs +C.sub.gd) (1)
and EQU f.sub.max =f.sub.t /2[G.sub.ds (R.sub.g +R.sub.s)+2.pi.f.sub.t C.sub.gd R.sub.g ].sup.5 (2)
where g.sub.mi is the intrinsic transconductance, C.sub.gs is the gate-to-source capacitance, C.sub.gd is the drain-to-gate capacitance, G.sub.ds is the output conductance, R.sub.g is the gate resistance, and R.sub.s is the source resistance. Thus increasing C.sub.gs degrades both f.sub.t and f.sub.max. Further, to realize an optimum f.sub.max, the output conductance, G.sub.ds must also be minimized while maintaining f.sub.t. This problem becomes more severe as the gate length of the transistor is reduced since carrier confinement is more difficult to realize, thus requiring an increased dose for the buried p-implant that in turn will degrade the high-frequency performance.
The inherent conflict in optimizing both DC and high-frequency performance is illustrated in a study by K Onodera, et al., (IEEE Trans. Electron Device, Vol. 38, No. 3, pp. 429-436, 1991). The authors there reported that in the case of two Be-implant doses used to form a buried p-region in GaAs MESFETs, the gate-to-source capacitance (C.sub.gs) increased at the higher Be dose (4.times.10.sup.12 cm.sup.-2 compared to 2.times.10.sup.12 cm.sup.-2 at 50 keV) thus degrading the unity current gain cutoff frequency (f.sub.t) and the maximum oscillation frequency (f.sub.max). The DC MESFET performance was enhanced by the high Be dose implant as demonstrated by a decrease in output conductance (g.sub.gs), but high-frequency performance, for reasons stated above, diminished. Prior to the invention disclosed herein, one way of dealing with this situation has been to construct devices wherein the buried p-implant is completely depleted of free carriers to minimize the junction capacitance while achieving good electron confinement in the channel. For conventional p-type implants (Be or Mg), however, neither the DC nor the high-frequency performance is optimized under this condition.
FIG. 1 is presented in order to provide a foundation for later discussion regarding the application and utility of the invention. The figure illustrates in a simplified flow diagram the prior art with respect to the primary steps in the process sequence for an all implanted, self-aligned GaAs n-channel metal semiconductor field effect transistor (nMESFET). The overall method for fabricating a GaAs MESFET is well known (see, for example, J. P. de Souza and D. K Sadana, IEEE Trans. Electron Dev., Vol. 39, pp. 166-175,1992 or M. J. Howes and D. V. Morgan, eds., Gallium Arsenide: Materials, Devices, and Circuits, pp. 361-427). It should be understood, though, that an implanted MESFET is only one device in which the present invention has utility. The principles of C-ion implantation described in this patent will also apply to other semiconductor devices such as junction field effect transistors (JFETs), heterostructure field effect transistors (HFETs), and high electron mobility transistors (HEMTs). In addition, non-self-aligned transistor structures that incorporate an implanted channel region will also benefit from this invention.
FIG. 1 (a) depicts GaAs substrate material (5) onto which a photoresist (20) is patterned to define a region into which ions are to be implanted. First, according to the prior art, a buried pregion (10) is created by implanting .sup.9 Be or .sup.24 Mg ions using ion implantation methods well-known to those skilled in the art of semiconductor device manufacturing. An n-channel (15) is then implanted above the buried p-region, typically using .sup.29 Si ions. Referring now to FIG. 1 (b), a gate metal contact (18) made from material such as tungsten, tungsten silicide, tungsten nitride or titanium nitride is deposited in contact with the n-channel previously formed. (The figure depicts the situation in which the photoresist (20) is removed. The decision as to whether to remove or to repattem the photoresist will depend on the final configuration of layers desired with respect to any particular application. As with implantation, use of photoresist masking is well established and known to those practicing the art.) FIG. 1(c) depicts a second implantation step performed using .sup.29 Si ions to form the n+ source (30) and drain (35) regions of the transistor. Following this step, and after the photoresist removal, the implants are all annealed (typically between 800 and 850.degree. C. for 10 to 60 seconds) to electrically activate the implanted species. Finally, as represented in FIG. 1 (d), ohmic source and drain contact metallization (40) is patterned, formed and alloyed.
The role of the buried p-implant is to improve the confinement of electrons in the MESFET channel. Confinement is realized by sharpening the profile of the silicon channel implant and providing a nip junction barrier to electron flow out of the bottom of the channel. The sharpening of the Si-channel implant is seen in simulated ion and carrier profiles such as are depicted in FIG. 3 (which is discussed more in detail, below, in the Detailed Discussion). This sharpening typically is accomplished by implanting acceptor atoms such as Be or Mg in the region just below the Si-channel. A drawback associated with this practice, however, concerns the fact that many of those atoms come to rest beyond the tail of the Si-channel and become active acceptors increasing C.sub.gs, and robbing the device of its high-frequency efficiency. This problem, however, is overcome by the method of the present invention, wherein C-ions are implanted in the place of Be, Mg or other similar acceptor atoms.
Although the use of C to modify Si-implant profiles has been reported (B. P. Davies, P. Davies, D. M. Brookbands, D. J. Warner, and R. H. Wallis, "Anomalous Behavior of Carbon Implants in Si-Doped GaAs," Int. Sum. GaAs and Related Compounds, pp., 275 -280,1990; R. M. Gwilliam, R. J. Wilson, T. D. Hunt, and B. J. Sealy, "The Use of Multi-Species Implantation for Carrier Profile Control in GaAs MESFETs Fabricated Using Silicon Ion Implantation," Nucl. Instr. and Methods in Phys. Res., B74, pp. 94-97, 1993), the unique feature relating to enhanced high-frequency performance is new with this invention. These references point to the efficiency of carbon as a compensator when implanted in silicon-oped GaAs material, specifically with respect to compensating the tail of the Si-implanted channel to produce sharper channel profiles. It is also known that carbon has a low activation efficiency. An important feature of the present invention concerns the distinctive characteristic of C wherein it exhibits low activation as an implanted acceptor by virtue of the fact that it occupies an As-site within the GaAs substrate matrix. Furthermore, the prior art does not incorporate this principle in semiconductor device structures to enhance performance.